Certain "pre-programmed" ICs have a regularly repeated or ordered physical structure. For instance, ROMs, speech synthesizers and melody synthesizers include a number of regions which can be divided into two-dimensional arrays of cells. Each cell within a specific region has a very similar physical structure. For example, FIG. 1 shows part of the design of a layout of a ROM IC 10 called a "code layer". (Herein, "layout" means the physical location and arrangement of IC components and regions on a physical layer of an IC chip. "Design" means a geometrical description of the physical locations of components and regions of a layout.) The code layer includes, an X decoder region 20, a Y decoder region 30 and a memory array region 40. Each of these regions 20, 30 and 40 has a regular, two-dimensionally repeated order. For instance, the memory array 40 has four sub-arrays 41, 42, 43, and 44. Each sub-array 41, 42, 43, and 44 is divided into eight areas b0, b1, b2, b3, b4, b5, b6, and b7. Each of the areas b0-b7 contains a row-column layout of storage cells, e.g., 40-0-0, 40-0-1, . . . , 40-1-0, . . . , which store bits of the eight bit data words stored in the memory array 40. Each area b0-b7 has cells for storing one particular bit of the eight bits of each eight bit data word. There are 128 cells in the x (horizontal) direction in each area b0-b7 (for storing one bit of each of 128 eight bit data words) and 256 cells in the y (vertical) direction in each area b0-b7 of each sub-array 41-44.
The above-mentioned IC devices (ROM, speech synthesizer, etc.) are "pre-programmed" in the sense that they are fabricated by introducing variations into a general layout design, such as the general ROM layout design 10 shown in FIG. 1. For instance, the ROM IC 10 is designed using the general ROM IC model 10. The ROM 10 permanently stores particular data in corresponding cells 40-0-0, 40-0-1, . . . , 40-1-0, . . . , etc. The permanent storage of data is achieved by varying the fabrication of each cell depending on whether a logic `1` or a logic `0` is to be stored in the corresponding cell. The particular variations in the fabrication of the cells depend on the type of ROM characteristics (e.g., cost, speed, power dissipation) desired in the design. For instance, according to one cell architecture, a transistor is placed in each cell that stores a logic `1` bit and no transistor is placed in each cell which stores a logic `0` bit. According to an alternative architecture, a transistor may be placed in each cell. However, those cells which store a logic `1` bit are fabricated (i.e., using an ion implantation fabrication step) so that they are permanently turned on while the cells which store a logic `0` bit are fabricated so that they are permanently turned off. In yet another alternative architecture, the storage of logic `1` and `0` bits is achieved by contact programming, i.e., by connecting the cells which store one logic bit value (e.g., logic `1`) to the word and bit lines but not connecting the cells which store the other logic bit value (e.g., logic `0`).
The task of designing a ROM, speech synthesizer, melody synthesizer, or other regularly ordered pre-programmed IC is often divided into a circuit design task and a programming task. For example, in the design of the ROM IC 10, circuit designers design the layout of the regions and components (e.g., the cells) on each physical layer of the IC chip. In designing the model ROM IC layout, the circuit designers determine the number of bits per addressed data word, the number of addressed data words, the total number of addresses and address bits and how those address bits are allocated to the X decoder and Y decoder for addressing individual cells of the layout. After making these determinations, the circuit designers draft a code layer which includes a design of the layout of regions and components on a physical layer, or physical layers, of the pre-programmed IC chip. In particular, the code layer includes a design of the layout of polygons corresponding to each cell of the pre-programmed IC chip at their respective physical locations on the physical layer or layers of the pre-programmed IC chip. Advantageously, the "design" is in the form of a database. The circuit designers typically write a new computer program in the C computer programming language for generating the code layer of each specific pre-programmed IC chip.
After completing the code layer, the circuit designers determine the mapping between addresses of addressed cells (which each correspond to one bit) and their corresponding cells. The circuit designers file a document with the programmers indicating the mapping relationships between addresses of cells and the cells themselves as laid out on the physical layer or layers of the ROM IC. The programmers study the code layer and mapping relations in order to discuss with the circuit designers the suitability of the physical implementation of the pre-programmed IC chip for a particular application. Because of the complexity of the mapping relations, the mapping relations are both difficult to document accurately and to understand. As a result, a long time is usually expended in reaching a consensus between the circuit designers and the programmers regarding the design of the pre-programmed IC chip. When a consensus is reached, the programmers introduce design variations into the code layer to suit a particular application. In the case of a ROM IC, the design variations are introduced (for producing appropriate physical variations as described above) in order to form a pre-programmed IC chip design which stores particular data. Again, this is achieved by modifying the specific C computer program used to generate the code layer.
Afterward, the database of the code layer is merged with the database of the other physical layers of the pre-programmed IC chip to form a complete chip layout design database. Thereafter, the complete chip design thus formed by the merger may be verified using a layout editor or by examining the whole chip layout design. If the layout of all of the physical layers of the ROM IC do not match each other, the layout is determined to be defective and is sent back to the design process for correction.
The problem with the conventional design approach is that it is time consuming and error prone. Both circuit designers and programmers must generate many lines of C computer program code which is both tedious and difficult to analyze. Because many lines of computer code are required, and because complex mapping relationships are often employed, errors can occur very easily but are difficult to locate and correct. Furthermore, simple conceptual changes in the design can lead to many computer code line changes.
It is therefore an object of the present invention to overcome the disadvantages of the prior art.